Coding of video signals for motion picture images is one type of video signal processings. For the purpose of compressing motion picture images, a motion compensation processing, a discrete consine transfer (DCT) processing, a quantization processing, etc. are utilized. The detail of these processings are described in the chapter 7 of Multi-Dimensional Signal Processing published by Nikkan Kogyo Shinbun.
In the motion compensation processing, block matching is realized between picture image regions to detect the motion of an object among consecutive frames. A fundamental processing P which is carried out for the block matching is expressed by an equation (1). EQU P=.SIGMA..vertline.a-b.vertline. (1)
For a high speed calculation method of the DCT processing, an FCT processing is utilized. This is a processing, in which several kinds of butterfly calculations are utilized as fundamental calculations. One of the butterfly calculations is expressed by an equation (2). ##EQU1## where "a" and "b" are signals to be processed. The detail of the FCT processing is described in a preparatory report entitled "Discrete Cosine Transfer Coding on the Video Signal Processor" of the national convention for 70 year anniversary of "the Institute of Electronics Informations and Communications Engineers".
For a reverse processing of the quantization processing, a reverse quantization processing is utilized. In the reverse quantization processing described in the revision of the recommendation H 261 for a visual telephony coding system of p * 64 Kbps by the CCITT, and equation (3) which is a fundamental calculation is utilized. ##EQU2##
The detail of the reverse quantization processing is described in "CCITT SGXV WP XV/1 Specialists Group on Coding for Visual Telephony, Doc. No 584, 1989".
Next, one of conventional arithmetic logic unit which is described in the Japanese Patent Provisional Publication (Kokai) No. 61-296427 will be explained. The conventional arithmetic logic unit comprises an arithmetic logic circuit for carrying out logic calculations of AND, OR, exclusive OR, and others between first and second input signals A and B to be expressed by complements of 2, an adding calculation of the first and second input signals A and B, and a subtracting calculation of the second input signal B from the first input signal A, a subtracting circuit for subtracting the first input signal A from the second input signal B, and a selecting circuit for selecting one output signal from output signals of the arithmetic logic circuit and the subtracting circuit.
In operation, the calculation of absolute value .vertline.A-B.vertline. for the difference between the two input signals A and B, etc. are carried out, although the detail of the operation will be explained later.
According to the conventional arithmetic logic unit, however, there is a disadvantage in that the aforementioned equations (2) and (3) can not be conducted by a single command, because it is fixed that the aforementioned equation (1) is conducted by one command.